The invention relates to the field of electronic circuits, and, more particularly, to a filter.
The Integrated Services Digital Network (ISDN) is an all digital communication network that allows for the transmission of voice, data and video using a bandwidth 3 kHz wider than the analog telephone bandwidth. The transmission is at a rate of 144 kbps using voice/data B channels. The basic idea of this type of network is to move the analog-digital conversion point from the exchange to the subscriber. The signal transmitted on a standard copper cable is thus a digital signal. With the basic access throughput, each subscriber terminal is connected to the exchange through two B channels and one D channel (2B+1D). For this basic access, each B channel carries a 64 kbps data stream, and the D channel carries a throughput of 16 kbps.
An ISDN structure for a basic access connection includes a line termination LT, a network termination NT, a U interface that forms the link between the LT and NT terminations, and at least one terminal equipment TE. The line termination LT performs the transmitting and receiving function for the 2B+D channels exchanged between the exchange and the user equipment by adapting the data format typical of the U interface with the data format of the exchange internal bus.
Digital transmission on copper loops with two wires has improved in recent years with a U interface, particularly with an ISDN access reception at the basic throughput. The ANSI standard requires an integral duplex type data transmission at 160 kbits/s using a 2B1Q type line code with echo suppression and time extraction. The transmitting and receiving clocks are synchronous at the network termination NT end, but a robust algorithm is necessary at the line termination LT end to synchronize received data with the transmitted data. For future applications, it is desirable that the phase difference between the transmit clock BCLK and the receive clock RXBCLK be stored so that the transit time can be precisely measured.
When implementing a phase lock loop PLL for phase extraction, the error in estimating the sampling phase is entered into a clock generation block to adjust the phase of the clock used for reduction of the received signal. In a prior art device, as shown in FIG. 1, a sigma-delta type digital/analog converter 10 includes an integrator 11 and an analog/digital converter 12 (threshold quantification, 1 bit) to output a sample at an oversampling frequency that is fixed with the signal output by a clock generation circuit. This converter 10 is followed by a low pass decimation filter 13.
The transfer function of this filter is as follows:             (              1                  1          -                      z                          -              1                                          )        3    ⁢            (              1        -                  z                      -            OVS                              )        3  
The variable ovs is the oversampling factor, and for example, ovs may equal 192. The decimation filter 13, the structure of which is shown in FIGS. 2A, 2B and 2C, performs a moving average of 192 input samples to one bit. The decimation filter 13 also supplies the band limitation function necessary to limit parasitic end coupling and quantification noise. This type of structure is reliable and has low power consumption.
FIGS. 2A, 2B and 2C are three equivalent representations. The low pass filter 20 in FIG. 2A is respectively replaced in FIGS. 2B and 2C by an integrator 21, 21xe2x80x2 and a differentiator 22, 22xe2x80x2 located on each side of an undersampling module 23. Thus, the integrators 21, 21xe2x80x2 used at the oversampling throughput are followed by a decimation module 23, 23xe2x80x2 and then a differentiation module 22, 22xe2x80x2.
During the undersampling process, the clock sampling phase is adjusted by the time extraction algorithm. This type of characteristic requires a parallel structure to avoid extraneous output overshoots which require a long set up time for high order filters. The straightforward approach shown in FIG. 3 includes two parallel channels at the output of the integrator 21. Each channel includes an undersampling module 23, 23xe2x80x2 followed by a differentiator 22, 22xe2x80x2 to output a reliable output sample. The sample is switched onto a channel that does not vary in time when the direct channel has to make a phase skip. The channel thus avoided can only be reused after the set-up time, which depends on the filter order. When a third order filter is used, the set up time is equal to three clock periods.
An article titled xe2x80x9cA Digital Signal Processor For An ANSI Standard ISDN Transceiverxe2x80x9d by Agazzi et al., and published in the IEEE Journal of Solid-State Circuits, Volume 24, No. 6, December 1989, pages 1605-1611, describes a digital signal processing module for an ISDN transmitter according to the American National Standards Institute (ANSI) standard. This module is similar to a multiprocessor architecture in which each processor is optimized. Another article titled xe2x80x9cTwo-Phase Decimation And Jitter Compensation In Full-Duplex Data Transceivers,xe2x80x9d by Agazzi et al., and published in IEEE, 1992, pages 1717-1720, describes a two-phase decimation technique. When this technique is combined with a known jitter compensation technique, it can maintain the performance of the echo emulator in a full duplex data transmitter in the presence of phase skips generated by the phase locking and clock extraction loop, and fast changes in the input signal sampling phase.
An object of the present invention is to provide a decimator filter that provides a phase extraction algorithm while avoiding instability of the delta-sigma converter due to adjustment of the sampling phase. More particularly, the decimator filter has application for digital phase extraction with a granularity or minimum precision of 1 ns in modems with an Integrated Services Digital Network (ISDN) U interface.
The decimator filter includes at least three identical undersampled filters out-of-phase with each other and connected in parallel, and an interpolator connected to the output of each filter. In one embodiment, the decimator filter includes a triple integrator having an output connected to each of the filters. Each filter defines a channel that includes in sequence an undersampling circuit, a differentiator and a multiplier. The outputs of the multipliers are connected to an adder. The input signals to each of these channels are offset by a delay equal to one period of the oversampled frequency. Each undersampling circuit and each multiplier has a second input receiving a signal from a state machine.
In another embodiment, the decimator filter includes a triple integrator followed by a first phase shift register with at least three positions equal to the number of channels connected to the first inputs of a demultiplexer. The outputs of the first phase shift register are connected to the first inputs of a subtracter through a second phase shift register, and to the second inputs of the subtracter. The outputs from the subtracter are connected to the second inputs of the demultiplexer, and to a third phase shift register with at least three positions related to a dichotomizing adder.
The interpolator is used to choose the sampling instant with a resolution equal to 1/64 of the period of the output sampling clock. The decimator filter according to the present invention improves the required phase extraction time and the precision defined in the ISDN U interface specifications. By combining the decimation filter and the extraction functions, a device is produced in a small area, which consequently, consumes low power.